In the fields of semiconductor integrated circuit devices which are applied particularly as required for high speed workability, it is usual to employ ECL/CML bipolar semiconductor integrated circuit devices. In the ECL/CML circuits, when power consumption and logical amplitude are made constant, the operating speed is determined depending on the parasitic capacitance of elements and interconnections which constitute the circuit and the base resistance and the gain-bandwidth product of a transistor. Of these, for the reduction of the parasitic capacitance, it is necessary to reduce the junction capacitance between the base and the collector of the transistor which greatly contributes to the operating speed. To this end, it is effective to use polysilicon in order that a base electrode is lead out to outside an element region thereby reducing the area of the base. In addition, it is generally adopted to use a method wherein polysilicon resistors and interconnections are formed on a thick field oxide film to reduce the parasitic capacitance thereof.
On the other hand, for the reduction of the base resistance, it is necessary that an extrinsic base layer be made low in resistance and is provided as closely to the emitter as possible and also to make the emitter shallow so that an intrinsic layer beneath the emitter is reduced with respect to the resistance. In order to enhance the gain-bandwidth product, it is effective to make a shallow junction between the emitter and the base along with a thin epitaxial layer of the collector.
As a prior technique which has been proposed for the purpose of realizing these modifications, a fabrication method disclosed in Japanese Patent Application No. 62-095358 is described.
FIGS. 4(A)-(F) are, respectively, sectional views of the steps of the technique. FIG. 5(a)-(f) are, respectively, enlarged views of peripheries of base and emitter regions for illustrating the steps of FIGS. 4(C)-(F) in more detail. It will be noted that part of the films is omitted in order to avoid complication of the drawings.
FIG. 4(A) shows a state wherein after element isolation, an about 3,000 angstrom thick polysilicon is formed and oxidized at approximately 200 angstroms on the surface thereof (not shown), followed by a selective formation of 1,000-2,000 angstrom thick nitride film at portion where a base electrode and a collector electrode are to be formed. Indicated at 401 is a P.sup.- -type silicon substrate, at 402 is an N.sup.+ -type buried diffusion layer formed on the silicon substrate 401, at 403 is an N.sup.- -type epitaxial layer formed on the buried diffusion layer 402, at 404 is an element isolation oxide film formed on the silicon substrate 401 and the buried diffusion layer 402, at 406 is polysilicon formed on the epitaxial layer 403 and the element isolation oxide film 404, and at 407 is a nitride film formed on the polysilicon 406.
Next, as shown in FIG. 4(B), the polysilicon 406 is selectively oxidized to form polysilicon regions 406a, 406c and 406d. Reference numeral 409 indicates an oxide film of the polysilicon 406. Subsequently, the nitride film 407 on the collector electrode is selectively removed and phosphorus is subjected to ion implantation into the polysilicon 406d of the collector electrode and thermally treated to form an N.sup.+ -type region 405 for reduction of the resistance of the collector. Thereafter, boron is ion implanted into the base electrode polysilicon 406a, 406c through the nitride film 407 at approximately 1-5.times.10.sup.15 cm.sup.-2, followed by annealing at a temperature of approximately 900.degree. C., thereby uniformizing the concentration of the boron in the base electrode polysilicon 406a, 406c. Then, the emitter-forming region of the polysilicon oxide film 409 is selectively removed and the inner wall is oxidized to form an approximately 200 angstrom thick inner wall oxide film 414. Through diffusion from the polysilicon 406a, 406c, a P.sup.+ -type extrinsic base 410 is formed. This state is shown in FIGS. 4(C) and 5(a).
Next, BF.sup.2 is ion implanted at approximately 1-5.times.10.sup.13 cm.sup.-2 to form an active base 411, after which as shown in FIG. 4(D) and 5(b), an approximately 1,000 angstrom thick oxide film 415 and an approximately 2,000 angstrom thick polysilicon 416 are formed by CVD over the entire surface. It will be noted that in FIG. 4(D), the oxide film 415 formed by CVD is not shown.
Subsequently, reactive ion etching is used to etch the polysilicon 416, followed by further etching of the oxide film 414, 415 to make an opening in the emitter as shown in FIGS. 4(E) and 5(c). The polysilicon 416 and the CVD oxide film 415 are left only on the side walls as shown in FIG. 5(C), thereby allowing an emitter, which is smaller than the opening of the nitride film 407, to be self-alignedly opened. At the same time, as shown in FIG. 4(E), the collector electrode polysilicon 406d is exposed.
Next, as shown in FIG. 5(d), an approximately 3,000 angstrom thick polysilicon 417 is deposited over the entire surface and after oxidation of the surface thereof in approximately 200 angstroms in thickness, arsenic is ion implanted at approximately 10.sup.16 cm.sup.-2.
As shown in FIG. 5(e), the oxide film 418, the polysilicon 417 and the nitride film 407 are etched, followed by thermal treatment to form an emitter 412 in the intrinsic base 411 by diffusion from the polysilicon 417.
A thin oxide film 418 is removed from the polysilicon 406a, 406c and 417, after which platinum is vacuum deposited, followed by thermal treatment to form a platinum silicide 419 on the surfaces of the polysilicon. At portions such as of a resistor which do not undergo any silicidation, the thin oxide film is left as it is. The platinum left unreacted on the oxide film is removed by aqua regia. Then, a CVD oxide film is deposited over the entire surface as shown in FIG. 5(f).
Finally, as shown in FIG. 4(F), contact holes are made to form an interconnection 413.
As described hereinabove, according to the fabrication method of the above technique, the emitter is formed in the selective oxide region of the polysilicon and the highly concentrated extrinsic base is formed through diffusion from the polysilicon left adjacent to the oxide region, so that the distance between the highly concentrated extrinsic base and the emitter can be significantly reduced. This allows easy formation of the emitter which is smaller in width than one attained by a minimum dimension of design. In addition, since the surface of the polysilicon with which the base electrode is brought to outside of the element region is converted to a silicide to an extent near the emitter and is thus rendered low in resistance, the base region is sufficient to be three times the minimum dimension of design, so that the base-collector junction capacitance can be reduced. Almost all the emitter junction is a junction with the intrinsic base with a low concentration, leading to the reduction of the emitter-base junction capacitance with the aid of the reduction in the width of the emitter.
Because the maximum depth of the junction can be made at not larger than 0.3 .mu.m, the epitaxial layer can be made as thin as 1 .mu.m or below, thereby shortening the transit time of the carrier through the depletion layer of collector. Moreover, the reduction in the junction capacitance results in shortage of the time constants of the collector and the emitter, thereby improving the gain-bandwidth product. Since, as described above, the base resistance and the parasitic capacitance of the transistor can be reduced and the gain-bandwidth product can be improved, remarkable speeding up can be achieved.
However, for the construction of high speed large capacity information communication systems, it is essential to realize high speed high integration LSIs of the analog digital hybird type. To this end, complementary devices are essential. In the above technique, for example, where a PNP transistor is used in combination with an NPN transistor used as a main element, it is inevitable to select:
(1) a lateral PNP transistor which has a structure of an NPN transistor from which an intrinsic base is eliminated and which includes one of P.sup.+ -type diffusion layers (an extrinsic base of the NPN transistor) as an emitter, the other as a collector, and an N.sup.- -type epitaxial layer (a low concentration collector of the NPN transistor) as a base:
(2) a vertical PNP transistor which has a structure of an NPN transistor from which an emitter is eliminated and which includes a P.sup.+ -type diffusion layer (a base of the NPN transistor) as an emitter, an N.sup.- -type epitaxial layer (a low concentration collector of the NPN transistor) as a base and a substrate as a collector; and
(3) a complementary transistor wherein emitters, bases separately formed through ion implantation masking using a photoresist. With (1) and (2), however, since the gain of the PNP transistor is small, matching in characteristics between the NPN transistor an the PNP transistor is not possible. With (3), it involves the problem that as a photoetching step increases, the productivity (yield, throughput) is lowered, thus impeding realization of highspeed high integration LSIs of the analog digital hybrid type.
In the fields of semiconductor integrated circuit devices requiring the high speed high integration. Consideration is generally given to MOS devices. Because of the fineness of the element, the device not only improves the scale of the integration, but also can reduce the speed-power product according to the scaling rule. The improvement of the integration scale brings about an effect of reducing the delay of interconnection accompanied by the shortage of critical path of the interconnection within integrated circuits, thus leading not only to the high operating speed of the element, but also to an improvement in the operating speed of the integrated circuit as a whole.
Since such high speed and high integration brings about the miniaturization and high performance of the devices in the applied fields, lower consumption power becomes important. As a consequence, the main current of MOS devices are now being changed to CMOS (complementary MOS) devices.
However, recent approaches to scaling down of the MOS devices depend on the photoetching technique and particulary, on the exposure technique. As a pattern size comes close to a wavelength of exposure light, studies have been made on utilization of light with a shorter wavelength (Deep-UV coherent light, X-rays) and charged particles (EB: electron beam, FIB: focussed ion beam). However, the utilization of such light rays inevitably need a large-sized (high cost) exposure apparatus and lowers productivity (throughput), making the practical utility difficult and thus producing an obstacle on the scaling down.
As a measure for solving the above problem, the present applicant disclosed a technique in a previous patent application, which is now described hereinbelow. FIGS. 2 are sectional views of steps of the technique and the steps are illustrated one by one.
(a) First, boron and arsenic are diffused in a P-type silicon substrate 201 having a crystal plane of 111 to form a P.sup.+ -type diffusion layer 202 with 800-1000.OMEGA./.quadrature. and an N.sup.+ diffusion layer 203 with 20-30.OMEGA./.quadrature.. Thereafter, an N.sup.- epitaxial layer 203 with 5-10.OMEGA./.quadrature. is grown in a thickness of about 0.8 .mu.m. The silicon substrate is oxidized to form an about 500 angstrom thick oxide film (not shown), on which an about 2000 angstrom thick nitride film (not shown) is deposited. The nitride film on the oxide film in a region on which an isolation oxide film is to be formed is removed, and the silicon substrate at the region is etched to a depth of about 4000 angstroms. Using a known high pressure oxidation technique, an about 1 .mu.m thick isolation oxide film 205 is formed. The nitride film is completely removed by etching with phosphoric acid. Thereafter, boron is ion implanted at a dose of 1-5.times.10.sup.15 ions/cm.sup.2 at an energy of 100 KeV, followed by thermal treatment at 1200.degree. C. to form a P well layer 222. After removal of the about 500 angstrom thick oxide film, a first polysilicon 206 having a thickness of about 3000 angstroms is deposited. The thermal oxidation at 900.degree. C. causes the surface of the polysilicon 206 to be converted to an about 200 angstrom thick oxide film 207. An about 500 angstrom thick nitride film 208 is deposited on the oxide film, followed by using a known lithographic technique to remove the nitride film 208 in regions for separation of electrodes and for a gate of the transistor.
(b) The polysilicon 206 which has not been covered with the nitride film 208 is thermally oxidized according to a known high pressure oxidation technique for conversion into an about 8000 angstrom thick oxide film 209. By utilizing a photoresist, arsenic is ion implanted into polysilicon 210 used as an N channel transistor electrode under conditions of 150 KeV and 1-5.times.10.sup.15 ions/cm.sup.2 and boron is ion implanted into polysilicon 211 used as a P channel transistor electrode under conditions of 100 KeV and 1-5.times.10.sup.15 ions/cm.sup.2. In order not to implant unnecessary ions, care should be taken such that when arsenic is ion implanted, the polysilicon 211 is covered with a photoresist and when boron is ion implanted, the polysilicon 210 is covered with a photoresist.
(c) The oxide film 209 which separates the N channel transistor electrode 210 and the P channel transistor electrode 211 therewith is covered with a photoresist, followed by removal of the other thick polysilicon oxide films by the use of hydrofluoric acid. After removal of the photoresist, thermal oxidation at 800.degree. C. is performed to form an about 200 angstrom thick oxide film 216. The regions on which the P channel transistor and the N channel transistor are to be formed are alternately covered with photoresists, followed by ion implantation of boron and arsenic successively under conditions of 40 KeV and 0.5-1.times.10.sup.12 ions/cm.sup.2. Annealing in an atmosphere of N.sub.2 at 800.degree.-900.degree. C. allows formation by diffusion of source and drain regions 212 and a channel region 213 of the N channel transistor, source and drain regions 214 and a channel region 215 of the P channel transistor.
(d) Using a known LPCVD technique, an about 1000 angstrom thick oxide film 217 is grown up, followed by growth of second polysilicon 218 with a thickness of about 2000 angstroms by the same method as indicated above.
(e) A gas mainly composed of CF.sub.4 is used for anisotropic etching of the second polysilicon 218 and the oxide films 217, 216 according to a known reactive-ion-etching method wherein the nitride film 208 and the single crystal silicon of the substrate serve as a stopper for the etching, thereby obtaining a configuration shown in the sectional view of this figure.
(f) By thermal oxidation at 800.degree. C., an about 150 angstrom thick gate oxide film is formed along with the second polysilicon 218 at the side walls being oxidized. Third polysilicon 220 is subjected to LPCVD in a thickness of about 3000 angstroms. The polysilicon in the P channel transistor region is covered with a photoresist, under which arsenic is ion implanted. The ion implantation conditions include 40 KeV and 1.times.10.sup.16 ions/cm.sup.2. Similarly, a photoresist is used to cover the polysilicon in the N-channel transistor region, under which boron is ion implanted under conditions of 40 KeV and 1.times.10.sup.16 ion/cm.sup.2. According to a known lithographic technique, the third polysilicon 220 and the nitride film 208 are patterned by dry etching. After annealing at 900.degree. C., an about 1500 angstrom thick oxide film is deposited according to LPCVD method. Openings are formed in part of the oxide film 221 on the third polysilicon 220 and the oxide films 221, 216 on the transistor electrodes 210, 211 according to a known lithographic technique, followed by sputtering of an aluminum-silicon alloy (not shown). Moreover, according to a known lithographic technique, the aluminum-silicon alloy is patterned and finally thermally treated at 500.degree. C. in an atomosphere of H.sub.2.
Features of the above technique reside in that the gate, source and drain regions are self-alignedly determined and that side walls are formed within the region where the selective oxide film of the polysilicon is removed, whereby a gate which is shorter in size than a minimum dimension of design can be formed.
In the above technique, however, when impurities are incorporated in the polysilicon serving as the source and drain electrodes and diffusion source, it is necessary to provide a masking for ion implantation such as by photolithography with respect to the N channel MOSFET and the P channel MOSFET. This presents a problem on the lowering of productivity (yield, thoughput) owing to the repetition of the photolithography procedure.
In addition, since any substrate (well) contact for giving a substrate (well) potential is not provided, limitation is placed on the range of application.
Further, since the electrodes of the gate, source and drain are formed of the polysilicon, a great resistance results. Accordingly, a great drop of voltage takes place owing to the passage of a great current at the time of switching, thus impeding an effect of improving the switching speed by the reduction in length of the gate.
The present invention has been accomplished in order to solve the above problems and has for its object the provision of a method for fabricating in high productivity (1) complementary bipolar transistors applicable to analog digital hybrid-type high speed integration LSIs and (2) complementary MOS transistors applicable to high speed high integration LSIs while removing the production and performance problems with respect to the formation method and structure of source drain electrodes.